Circuit for the generation of a scanning clock in an operational anaylsis device of the serial type for an integrated circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 15, 1993
Grant Date -
N/A
app pub date -
Dec 18, 1991
filing date -
Dec 19, 1990
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully