Bump coplanarity for semiconductor device assembly and methods of manufacturing the same
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United States of America Patent
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Aug 29, 2023
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app pub date -
Aug 21, 2020
filing date -
Aug 21, 2020
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Abstract
Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.
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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
MICRON TECHNOLOGY INC | 8000 SOUTH FEDERAL WAY BOISE ID 83716-9632 |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Lin, Ko Han | Taichung, TW | 2 | 1 |
Tsai, Tsung Che | Tainan, TW | 3 | 1 |
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