Automated network-on-chip design

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United States of America Patent

PATENT NO 11960815
APP PUB NO 20230145577A1
SERIAL NO

18092485

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.

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Patent Owner(s)

  • ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fink, Wolfgang Tucson, US 34 692

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