Input transition responsive CMOS self-boost circuit
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United States of America Patent
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Nov 3, 1992
Grant Date -
N/A
app pub date -
Sep 16, 1991
filing date -
Sep 16, 1991
priority date (Note) -
Expired
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Abstract
A CMOS self-boost circuit inclused a pull-up N-channel transistor (MN1 ), a self-capacitance (SC), an N-channel gating transistor (MN2), a pull-up P-channel transistor (MP1), and a pulse circuit (18). The pulse circuit is formed of the delay network and a NAND logic gate (ND1). The pulse circuit is responsive to an input control signal making a low-to-high transition for generating a pulse signal. The gate of the pull-up P-channel transistor (MP1) is responsive to the pulse signal for pulling up initially the gate of the pull-up N-channel transistor (MN1) close to an upper power supply potential, thereby rendering greater conduction of the pull-up N-channel transistor (MN1) to provide a higher output voltage corresponding to a high logic state.
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