Apparatus and method for obfuscating power consumption of a processor
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United States of America Patent
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Apr 9, 2019
Grant Date -
Dec 21, 2017
app pub date -
Jun 17, 2016
filing date -
Jun 17, 2016
priority date (Note) -
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Abstract
An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.
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