Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network
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United States of America
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Mar 10, 2020
Grant Date -
Jul 4, 2019
app pub date -
Mar 9, 2019
filing date -
Mar 9, 2019
priority date (Note) -
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Abstract
An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.
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