Importance

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Abstract

An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master latch, and further enables a multiplexer to select between the external and internal address inputs. In response to a subsequent rising edge of the system clock, the selected address input is then loaded into a low-output-load capacitance slave latch and is further provided to complementary output nodes. The signal from one of the output nodes is also fedback to circuitry for incrementing the selected address internally for subsequent clock cycles remaining in the burst mode operation. Once the initial address of the burst operation has thusly been entered, for the remainder of the burst mode, the multiplexer selects the address loaded into the internal address master latch and operates as an edge-triggered flip/flop with the master latch accepting an incremented address in response to the falling edge of the system clock and with the slave latch loading and outputting the incremented address in response to the rising edge of the system clock. During a standby mode, circuitry is provided for disabling the counter cell and ensuring that the output nodes are stable and disabled.

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First Claim