Method to enable the prevention of cache thrashing on memory management unit (MMU)-less hypervisor systems

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11232034
APP PUB NO 20210096899A1
SERIAL NO

16585507

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Abstract

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A cache circuit associated with a hypervisor system is disclosed. The cache circuit comprises a cache memory circuit comprising a plurality of cachelines, wherein each cacheline is configured to store data associated with one or more virtual machines (VMs) of a plurality of VMs associated with the hypervisor system and a plurality of tag array entries respectively associated with the plurality of cachelines. In some embodiments, each tag array entry of the plurality of tag entries comprises a tag field configured to store a tag identifier (ID) that identifies an address of a main memory circuit to which a data stored in the corresponding cacheline is associated and a VM tag field configured to store a VM ID associated with a VM to which the data stored in the corresponding cacheline is associated.

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Patent Owner(s)

  • INFINEON TECHNOLOGIES AG

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Harihar, Manoj Kumar Germering, DE 2 0
Ygnace, Romain Brunnthal, DE 35 194

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