Semiconductor device with improved overlay margin and method of manufacturing the same

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United States of America Patent

PATENT NO 7414279
APP PUB NO 20050173750A1
SERIAL NO

11049428

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Abstract

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Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

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Patent Owner(s)

  • SAMSUNG ELECTRONICS CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Park, Joon-Soo Seongnam-si, KR 23 380

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