Multi-gate device and related methods

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United States of America Patent

PATENT NO 11688736
APP PUB NO 20220231016A1
SERIAL NO

17657941

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Abstract

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A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chiang, Kuo-Cheng Hsinchu County, TW 394 306
Chuang, Li-Yang Hsinchu, TW 14 8
Wang, Chih-Hao Hsinchu County, TW 1024 6956
You, Jia-Chuan Taoyuan County, TW 97 199

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