Method of fabricating a vertically integrated memory cell
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 29, 2006
Issued Date -
N/A
app pub date -
Jun 22, 2004
filing date -
Aug 28, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers within the trench. A doped region is buried at the bottom of the trench. The structure can be fabricated such that the buried doped region provides a connecting layer in a multi-bit flash memory cell. Alternatively, the buried doped region may be used as a buried bitline in a single bit flash memory cell.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully