Clock control circuit and method
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United States of America Patent
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-
Aug 3, 2004
Issued Date -
N/A
app pub date -
Dec 30, 2002
filing date -
Apr 27, 2000
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 11.sub.1 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 11.sub.2 corresponding to the position on the forward route 11.sub.1. The timing difference between these clocks is averaged to output an averaged timing difference.
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