Arithmetic circuit with multiplexed addend inputs
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United States of America Patent
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Jan 20, 2009
Grant Date -
Jun 30, 2005
app pub date -
Dec 21, 2004
filing date -
Dec 29, 2003
priority date (Note) -
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Abstract
Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.
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