Semiconductor memory device having hierarchical bit line structure
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United States of America Patent
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-
Jan 2, 2007
Grant Date -
Jun 9, 2005
app pub date -
Nov 29, 2004
filing date -
Nov 28, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines corresponding to the memory array; a pair of global bit lines corresponding to the pair of local bit lines; a precharge circuit including an output terminal being connected to the pair of local bit lines; a local write amplifier circuit including a data input terminal being connected to the pair of global bit lines and an output terminal being connected to the pair of local bit lines; and a control signal line being connected to an input terminal of the precharge circuit and to a control input terminal of the local write amplifier circuit, wherein the local write amplifier circuit is deactivated by the control signal line when the precharge circuit is activated, and the precharge circuit is deactivated by the control signal line when the local write amplifier circuit is activated.
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