Scalable successive-approximation-register analog-to-digital converter

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United States of America Patent

PATENT NO 8779961
APP PUB NO 20130106638A1
SERIAL NO

13666251

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Abstract

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A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.

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Patent Owner(s)

  • MARVELL WORLD TRADE LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Castello, Rinaldo Arcore, IT 52 384
Cesura, Giovanni Antonio Cremona, IT 9 20
Rezzi, Francesco Cava Manara, IT 28 301
Sutardja, Sehat Los Altos Hills, US 552 7290

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