Method of wiring semiconductor integrated circuit and semiconductor integrated circuit

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United States of America Patent

PATENT NO 5872719
SERIAL NO

08691708

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Abstract

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In designing wiring for semiconductor integrated circuits, wiring channels are assigned to reduce a signal delay time developed parallel traces. The selection of the wiring channels for all of the wiring oriented nets of the circuits is based on the trunk trace length between the terminals. For the longer trunk trace lengths, a double-pitch wiring channel is assigned. First, the determined trunk-trace lengths are sorted in decreasing order of length. Then, a double-pitch wiring channel is assigned for the trunk-trace lengths that are greater than a predetermined length. When no double pitch channels remain, single pitch channels are used.

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Patent Owner(s)

  • HITACHI, LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kato, Naoki Kodaira, JP 177 1923
Miyazaki, Yoshiaki Hadano, JP 24 370
Suzuki, Katsuyoshi Hadano, JP 143 1609
Yamada, Hiromitsu Hadano, JP 8 89

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