Semiconductor device and method for lowering miller capacitance for high-speed microprocessors
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United States of America Patent
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Jun 1, 2004
Grant Date -
N/A
app pub date -
Feb 15, 2001
filing date -
Feb 15, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.
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