Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making
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United States of America Patent
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Feb 26, 2008
Grant Date -
Jun 15, 2006
app pub date -
Jan 12, 2006
filing date -
Jan 27, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory device including a substrate, and multiple self-aligned nano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.
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