Memory element, semiconductor device, and writing method

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United States of America Patent

PATENT NO 9190166
APP PUB NO 20140204649A1
SERIAL NO

14155790

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Abstract

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A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node.

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Patent Owner(s)

Patent OwnerAddress
SONY CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amari, Koichi Kanagawa, JP 25 71
Arima, Takayuki Kanagawa, JP 10 45
Kanda, Yasuo Kanagawa, JP 21 57
Tokitou, Shunsaku Kanagawa, JP 2 8
Torige, Yuji Kanagawa, JP 9 25

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