Collector tailored structures for integration of binary junction transistors
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United States of America Patent
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Dec 9, 2008
Grant Date -
Oct 25, 2007
app pub date -
Apr 19, 2006
filing date -
Apr 19, 2006
priority date (Note) -
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Abstract
A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is employed to implant a dopant into the target deep well region to form a deep well region with the selected region having a lowered dopant concentration. The lowered dopant concentration can yield a higher breakdown voltage for the bipolar device. The intrinsic dilute mask mitigates implantation within the selected region.
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