Output prediction logic circuits with ultra-thin vertical transistors and methods of formation
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United States of America Patent
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May 15, 2007
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Mar 16, 2005
filing date -
Jun 10, 2002
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Abstract
Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.
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