Mitigation of transistor reliability degradation within memory circuits

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11972823
APP PUB NO 20240087666A1
SERIAL NO

17942143

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A controller includes an interface and circuitry. The interface communicates with memory cells arranged in multiple address locations. Storage nodes holding storage values included in the memory cells are accessible using select transistors powered by an adjustable supply voltage. The circuitry reads data units protected by an Error Correction Code (ECC) from the memory cells and decode the ECC of the data units. Upon detecting, using the ECC, that a given data unit read from a given address location contains one or more errors, the circuitry logs an error event specifying at least a time of occurrence associated with the error event and the given address location. The circuitry identifies that the select transistors experience physical degradation due to aging, based on the times of occurrence and address locations logged in the error events, and adjusts the supply voltage provided to the select transistors to compensate for the physical degradation.

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Patent Owner(s)

  • APPLE INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shappir, Assaf Ganey Tikva, IL 43 384

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