Semiconductor device having a trench with a step-free insulation film
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United States of America Patent
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Aug 21, 2007
Grant Date -
Apr 21, 2005
app pub date -
Nov 10, 2004
filing date -
May 13, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A method of manufacturing a semiconductor device provided with a MOS field effect transistor having a channel region of a first conduction type formed in a surface layer portion of a semiconductor substrate, a source region of a second conduction type formed on a rim portion of a trench made to penetrate through the channel region, and a base region of the first conduction type formed in the surface layer portion of the semiconductor substrate adjacently to the source region. The method includes: a step of forming a mask layer having a base-region forming opening corresponding to the base region and a trench forming opening corresponding to the trench on the semiconductor substrate in which the channel region is formed; a base-region forming step of introducing impurities through the base-region forming opening; a trench forming step of forming the trench through the trench forming opening; and a step of forming a gate insulation film on an inner wall surface of the trench.
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