Method and apparatus for reducing timing pessimism during static timing analysis
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United States of America Patent
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Jun 26, 2007
Grant Date -
Apr 27, 2006
app pub date -
Oct 22, 2004
filing date -
Oct 22, 2004
priority date (Note) -
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Abstract
One embodiment of the present invention provides a system that reduces timing pessimism during Static Timing Analysis (STA). During operation, the system receives parametric variation data which describes the on-chip variation of timing-related parameters. Next, the system computes region-specific derating factors using the parametric variation data. The system then identifies a set of worst-case violating paths using the region-specific derating factors. Next, the system computes path-specific derating factors for one or more paths in the set of worst-case violating paths using the parametric variation data and the path properties. Finally, the system identifies zero or more realistic-case violating paths from the set of worst-case violating paths using the path-specific derating factors.
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