Low loss power device and method for fabricating thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11552194
APP PUB NO 20210376146A1
SERIAL NO

17179863

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Abstract

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Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to optimize device channel resistance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thin dielectric layer may be formed under an extension gate to reduce channel resistance. A thick dielectric layer may be formed under an extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

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Patent Owner(s)

  • METAMOS SOLUTIONS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Timothy Taipei, TW 44 878

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