Method and apparatus for instruction sampling for performance monitoring and debug
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United States of America Patent
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Jun 3, 2003
Grant Date -
N/A
app pub date -
Nov 4, 1999
filing date -
Nov 4, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for selecting an instruction to be monitored within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate instructions that are eligible for sampling. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. The matched instructions may be marked using a match bit that accompanies the instruction through the selection process. The instructions eligible for sampling are then sampled to generate a sampled instruction. A sampled instruction may be marked with a sample bit that accompanies the instruction through the instruction execution process in order to monitor the sampled instruction while it is executing within the pipelined processor.
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