Method and apparatus for data compression and decompression for a data processor system

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6484228
APP PUB NO 20020042862A1
SERIAL NO

10008074

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • FREESCALE SEMICONDUCTOR, INC.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Breternitz, Jr Mauricio Austin, TX 18 529
Smith, Roger A Austin, TX 120 2909

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation