Semiconductor package and method for manufacturing the same for decreasing number of processes
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United States of America Patent
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Jun 8, 2010
Grant Date -
Jan 29, 2009
app pub date -
Mar 7, 2008
filing date -
Jul 27, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern.
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