Reducing latency for memory operations in a memory controller
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United States of America Patent
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Sep 27, 2022
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N/A
app pub date -
Oct 20, 2020
filing date -
Oct 20, 2020
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Abstract
Disclosed in some examples are methods, systems, memory controllers, devices, and machine-readable mediums which minimize this stall time by returning a memory write acknowledgement once a write command has been selected by the memory controller input multiplexor rather than when the memory write command has been performed. Because the memory controller enforces an ordering to memory once the packet has been selected at an input multiplexor, ordering of prior and subsequent requests to the same address location are preserved and providing the response early allows the processor to continue its operations earlier without any harmful effects.
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