Method and apparatus for interface failure survivability using error correction

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7080288
APP PUB NO 20040216026A1
SERIAL NO

10425423

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ferraiolo, Frank David Essex Junction, VT 34 789
Floyd, Michael Stephen Austin, TX 74 1785
Reese, Robert James Austin, TX 16 436
Reick, Kevin Franklin Round Rock, TX 25 794

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