Semiconductor memory device and test method thereof

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United States of America Patent

PATENT NO 7054209
SERIAL NO

11134576

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Abstract

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A semiconductor memory device vice disclosed herein comprises: a memory cell array divided into a plurality of blocks, each of which includes a plurality of memory cells; a plurality of row decoders which correspond to the blocks, each of the row decoders including an access information holder configured to hold access information indicating whether its corresponding row decoder has been accessed; and an access information reader configured to read the access information held in the access information holders.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Imamiya, Kenichi Tokyo, JP 169 3270
Kawai, Koichi Kanagawa, JP 81 790

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