Test circuit and method for multilevel cell flash memory

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Jan 29, 2008
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Nov 17, 2004
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Nov 17, 2004

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Abstract

A test circuit is sued to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

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Patent Owner(s)

SILICON STORAGE TECHNOLOGY, INC.

International Classification(s)

G11C:STATIC STORES

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[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Hoang, Loc B	San Jose, CA	41	486
Ly, Anh	San Jose, CA	124	549
Nguyen, Hung Q	Fremont, CA	75	961
Nguyen, Sang Thanh	Union City, CA	45	480
Saiki, William John	Mountain View, CA	20	469
Sarin, Vishal	Cupertino, CA	182	2197
Tran, Hieu Van	San Jose, CA	336	3219

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Test circuit and method for multilevel cell flash memory

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United States of America Patent

10991702

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US Family Size	Non-US Coverage
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DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
January 29, 2008	US,7325177,B2 US7325177B2	GRANTED PATENT AS SECOND PUBLICATION
June 08, 2006	US,20060123280,A1 US20060123280A1	FIRST PUBLISHED PATENT APPLICATION

PATENT NO	7325177
SERIAL NO	10991702
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