Digital processing circuit having a multiplication function
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United States of America Patent
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-
Oct 8, 1985
Grant Date -
N/A
app pub date -
Feb 25, 1982
filing date -
Feb 25, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.
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