Identifying an optimizable logic region in a logic network
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United States of America Patent
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Jan 25, 2000
Grant Date -
N/A
app pub date -
Dec 9, 1996
filing date -
Dec 9, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to 'reconvergent fanout nodes'. A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.
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