Non-volatile electromechanical configuration bit array

United States of America Patent

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Feb 8, 2011
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May 24, 2007
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Nov 22, 2005
filing date
Nov 22, 2005

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Abstract

A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

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AGATE LOGIC, INC.;VENTURE LENDING & LEASING IV, V

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G11C:STATIC STORES

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Inventor Name	Address	# of filed Patents	Total Citations
Trossen, David Richard	San Jose, US	3	19
Wing, Malcolm John	Palo Alto, US	7	521

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Non-volatile electromechanical configuration bit array

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United States of America Patent

11285535

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PATENT NO	7885103
APP PUB NO	20070115713A1
SERIAL NO	11285535
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
February 08, 2011	US,7885103,B2 US7885103B2	GRANTED PATENT AS SECOND PUBLICATION
May 24, 2007	US,20070115713,A1 US20070115713A1	FIRST PUBLISHED PATENT APPLICATION

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11285535

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