Chip area optimization for multithreaded designs
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United States of America Patent
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Mar 3, 2009
Grant Date -
May 15, 2008
app pub date -
Nov 15, 2006
filing date -
Nov 15, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a set of connection points among the circuit components at which the processing stage may be split for addition of multithreading capability to the circuit. A subset of the connection points is selected, and splitter components are inserted at the connection points in the subset.
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