Silicon buffered shallow trench isolation
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 3, 2007
Grant Date -
May 5, 2005
app pub date -
Jan 12, 2004
filing date -
Jan 14, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is formed in a selective epitaxial growth (SEG) process. The SEG process can be a CVD or MBE process. Capping layers can be used above the strained silicon layer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully