Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure
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United States of America Patent
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Sep 2, 2014
Grant Date -
Oct 3, 2013
app pub date -
Mar 29, 2012
filing date -
Mar 29, 2012
priority date (Note) -
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Abstract
Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided.
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