Electronic assembly with sandwiched capacitors and methods of manufacture
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United States of America Patent
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May 31, 2005
Grant Date -
Jun 5, 2003
app pub date -
Dec 3, 2001
filing date -
Dec 3, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
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