Importance

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Abstract

A method includes performing a first etch process to form a via hole in a dual-damascene integrated circuit structure comprising a first dielectric layer and a second dielectric layer. The via hole extends at least substantially through the first and second dielectric layers. The method further includes filling at least a portion of the via hole with a plug material to form a plug within the via hole, and performing a second etch process through the first dielectric layer and the portion of the plug adjacent the first dielectric layer to form a trench in the first dielectric layer. The second etch process is performed using an RF power of less than 1,000 Watts and using an etching chemistry that includes CF.sub.4 and N.sub.2. For example, second etch process may use an etching chemistry of CF.sub.4/N.sub.2/Ar, which may additionally include one or both of CO and O.sub.2.

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First Claim