Run-time code parallelization with monitoring of repetitive instruction sequences during branch mis-prediction

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United States of America Patent

PATENT NO 9135015
SERIAL NO

14583119

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Abstract

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A method includes, in a processor that executes instructions of program code, monitoring the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions. In response to detecting a branch mis-prediction in the monitored instructions, the specification is corrected so as to compensate for the branch mis-prediction. Execution of the repetitive sequence is parallelized based on the corrected specification.

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Patent Owner(s)

  • CENTIPEDE SEMI LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Friedmann, Jonathan Even Yehuda, IL 47 611
Koren, Shay Tel-Aviv, IL 20 175
Mandler, Alberto Zichron Yaakov, IL 18 92
Mizrahi, Noam Hod Hasharon, IL 64 333

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