Wafer translator having a silicon core isolated from signal paths by a ground plane
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United States of America Patent
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Sep 7, 2010
Grant Date -
Sep 10, 2009
app pub date -
Mar 20, 2008
filing date -
Mar 7, 2008
priority date (Note) -
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Abstract
Apparatus and methods are provided for wafer translators having a silicon core, an isolating conductive ground plane, and copper and subjacent resin layers disposed on the ground plane. A silicon substrate having at least one major surface coated with an electrically conductive layer is subjected to a number of printed circuit board manufacturing operations including, but not limited to, application of resin-coated copper foils; mechanical grinding of copper layers; mechanical drilling of via openings in a dielectric material; plating of copper, nickel, and gold layers; laser removal of metal; and chemical removal of metal; in order to produce a wafer translator having a silicon core. In further aspects of the present invention, alignment marks are formed and contact structures, such as stud bumps, are placed relative to a local set of alignment marks.
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