Method and system to implement an improved floating point adder with integrated adding and rounding
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United States of America Patent
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Nov 8, 2005
Grant Date -
Jul 10, 2003
app pub date -
Jul 31, 2001
filing date -
Jul 31, 2001
priority date (Note) -
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Abstract
Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding, so that the final mantissa does not require processing by a follow on rounding stage.
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