Read-only memory construction and related method
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United States of America Patent
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Oct 8, 1985
Grant Date -
N/A
app pub date -
Jun 8, 1983
filing date -
Jun 8, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A read-only memory circuit having, for a given memory access time, a power requirement of approximately one half of the power requirement needed to allow for a worst-case condition in which all bit storage locations may be in a binary memory state requiring maximum power consumption. Information stored in each row of the memory circuit is selectively complemented to minimize the power consumption in the individual rows and columns. Tables are used to store complement indicators for the rows and columns, and decoding circuitry selectively complements data read from the memory circuit, in accordance with the stored complement indicators.
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