Encasing arrangement for a semiconductor component
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Apr 24, 2007
Grant Date -
Feb 24, 2005
app pub date -
Dec 13, 2000
filing date -
Dec 14, 1999
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.
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