Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system

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United States of America Patent

PATENT NO 5961621
SERIAL NO

08827540

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Abstract

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A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jayakumar, Muthurajan Sunnyvale, CA 15 344
MacWilliams, Peter D Aloha, OR 51 2226
Pawlowski, Stephen Beaverton, OR 12 217
Wu, William S Cupertino, CA 25 1125

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