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Abstract

Disclosed are methods for designing standard cell transistor layouts for minimizing transistor delays and for minimizing power consumption. The method of minimizing transistor delays includes defining a transistor model for a P-type transistor and an N-type transistor of a CMOS standard cell. The method then includes minimizing a ratio between the P-type transistor and the N-type transistor. The ratio is defined by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The optimizing is performed by substantially minimizing an average delay for the transistor structure. In this embodiment, the CMOS standard cell will define a transistor structure that is implemented to make a logic circuit. The CMOS standard cell is one of a library of standard cells, where each standard cell defines a particular logic circuit.

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First Claim