Method and apparatus for optimizing delay paths through field programmable gate arrays
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United States of America Patent
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Jul 24, 2007
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app pub date -
Aug 16, 2004
filing date -
Aug 16, 2004
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Abstract
A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.
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