Software-to-hardware compiler
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United States of America Patent
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-
Aug 14, 2007
Grant Date -
Jul 25, 2002
app pub date -
Aug 7, 2001
filing date -
Aug 7, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A hardware-to-software compiler is provided that runs an optimization on a circuit implemented in programmable logic. The optimization allows portions of the program implemented by the circuit to be executed via software. A communication interface between the hardware and software is provided that allows for efficient data flow. A communication channel is provided that can be effected as bidirectional using a unidirectional transport medium (e.g., PCI bus). Communication between devices is done through pop interface buffers and push interface buffers on either side of the communication channel.
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