Multiplexers for efficient PLD logic blocks
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United States of America Patent
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Oct 15, 2002
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N/A
app pub date -
Feb 20, 2001
filing date -
Feb 20, 2001
priority date (Note) -
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Abstract
A logic section of a programmable logic device comprising a first circuit and a second circuit. The first circuit may be configured to (i) implement user defined programmable logic and (ii) generate an output in response to a first input and a second input. The second circuit may be configured to generate the second input in response to the output, a third input, and a fourth input.
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